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The short answer: Embedded engineering hiring statistics point to a gap of about ten months. Technical roles take an average of 5.4 months to recruit and another 4.8 months to reach normal productivity (Linux Foundation, 2024). A requisition approved in January delivers full hours around November, so first-half 2027 milestones need the current team plus outside engineering hours.
Most 2027 engineering plans approve heads in January. The program asks for hours in March: board bring-up, a verification push on the first FPGA build, a customer milestone that was dated before anyone opened a requisition. The two sit in the same plan on different rows, and the gap between them has no row of its own. The Linux Foundation’s 2024 survey, a general tech sample, sizes it: an average of 5.4 months to recruit technical staff, then 4.8 more before a new hire reaches normal productivity. A requisition approved in January reaches full load around November.
Those are the hours nobody wrote down, and the senior engineers already on staff end up covering them while they interview and onboard the hire. Headcount is still the right answer for work that will exist in three years. Milestones due before July need the team already employed plus outside hours. Price those hours against what a one-quarter slip costs: deferred revenue, a customer schedule that moves with yours, a missed qualification or trade-show date, and another quarter of salaries spent reaching the same point.
The embedded engineering hiring statistics below cover hiring time, the hiring market, ramp, the load senior engineers already carry, Fidus’s own outside capacity, pay, and the choice between training, hiring and outside help. Every figure is linked or named at its original publisher, and the page was last updated on September 30, 2026.
Recruiting plus ramp is the gap. The other lines show what makes it hard to close.
How long recruiting takes depends on where you stop the clock. Neither survey reports embedded or FPGA roles separately, so the figures below cover technical roles and all roles.
SHRM’s clock stops at the accepted offer, so notice periods, relocation and the ramp all sit outside it. Both samples are broader than embedded engineering. Embedded and FPGA candidates come from a smaller pool, so expect those roles to run longer. The shortest number is the easiest one to put in a plan, and everything past it becomes hours nobody wrote down.
Recruiting runs long because the candidates are scarce.
The semiconductor and aerospace figures describe whole sectors, and those sectors hire from the same pool of FPGA, board and firmware engineers that an embedded team draws on. A requisition opened in January competes with every other program chasing mid-career hardware engineers that quarter. Recruiting is the part of the plan you control least. Don’t count on it for first-half hours.
An accepted offer doesn’t deliver hours. A new engineer learns the system from the senior engineers who already know it, in the months the program needs those engineers most.
While a new engineer learns unfamiliar boards, register maps and toolchains, a senior engineer spends part of every week teaching them. Those are hours the plan never wrote down. If the hire leaves in month five, the requisition reopens, the ramp restarts, and the senior hours are already spent. Next to each hire’s start date in the 2027 plan, name who carries the work if they leave.
The engineers who would interview, onboard and review a new hire are already carrying a late program. The verification data says most FPGA programs run behind.
A new engineer’s first blocks need closer review than a veteran’s, and that review comes out of the same verification hours. A program already behind absorbs a hire by falling further behind. That review time comes out of verification, already 42% of FPGA design engineers’ time in the 2022 study, and it falls to the people the milestone depends on.
Outside engineers are available in the months a new hire is still being recruited.
Outside engineers ramp too: they have to learn your system, and your architect spends time on the handover. An engineer who has worked on the same FPGA family and toolchain on other programs starts from experience a new hire would need months to build. That head start lets outside hours arrive inside the first half, while the gap in the plan is still open. Fidus’s guide to when outsourcing embedded software makes sense covers the skills, capacity, timeline and regulatory triggers.
A 2027 plan already carries pay and benefits. Those lines pay for the team you’ll have by the fourth quarter.
| Occupation (US) | Median annual wage, May 2025 | Source |
|---|---|---|
| Computer hardware engineers | $161,740 | BLS Occupational Outlook Handbook |
| Electrical and electronics engineers, combined | $125,040 | BLS Occupational Outlook Handbook |
| Electrical engineers | $120,630 | BLS Occupational Outlook Handbook |
A January hire’s salary starts when they do, and the full-load hours it buys arrive around November. Until then, the plan pays for hours it isn’t getting.
Asked how they would close their top skill gap, cloud skills, most organizations chose to train the people they already had. The split covers cloud skills only.
Upskilling fits when the new skill sits close to what the team already does and the work that needs it lands in the second half. For a first-half milestone it spends the unwritten hours twice: the engineer being trained is one of the people carrying the milestone, and the engineer training them is another. Some work needs a senior practitioner to lead it, such as a first 112G PAM4 design or a jump to an FPGA family with hardened AI engines. That work goes faster with an outside engineer leading and an internal engineer alongside, ready to own it by the second half.
Before the 2027 budget locks, list every first-half milestone and write beside each one the name of the engineer who carries it. Where the name belongs to an open requisition, that line is the gap nobody wrote down. It gets one of three decisions: move the milestone to the second half, cover it with outside hours priced against a one-quarter slip, or accept the slip in writing. Open the requisitions anyway for the work that will still exist in three years, and plan them to reach full load in the fourth quarter.
Fidus is a North American custom embedded systems design and services firm, with FPGA, hardware, embedded software, ASIC, signal integrity, and mechanical and thermal design in house. Its FPGA design services can carry a first-half milestone while the requisition fills, and under its First Time Right methodology the work comes back ready for your NPI process and for your own engineers to take over.
Neither major survey breaks out embedded or FPGA roles, but technical staff take an average of 5.4 months to recruit (Linux Foundation, 2024), and 64% of organizations need more than four months. SHRM’s 2025 median of about a month and a half stops the clock at offer acceptance, so it leaves out notice periods, relocation and ramp.
New technical hires take an average of 4.8 months to reach normal productivity, and at 58% of organizations it takes more than four months (Linux Foundation, 2024). Senior engineers spend part of that time teaching the system, which comes out of their own program hours.
Yes. The SIA and Oxford Economics project that 67,000 US semiconductor jobs risk going unfilled by 2030, including 27,300 engineering roles. BLS projects 9% growth in computer hardware engineering jobs from 2025 to 2035, and 76% of aerospace and defense companies name engineering as their biggest hiring challenge (AIA and McKinsey, 2025).
The US median annual wage for computer hardware engineers was $161,740 in May 2025 (BLS). Benefits add roughly 30% of total compensation cost in private industry (BLS, June 2026).
Outside engineers fit milestones due before a new hire would reach full load, which is roughly the first half of the year for a January requisition. Hiring still fits work that will exist in three years. Price the outside hours against what a one-quarter slip would cost.
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