112G PCB Design: Where Your PAM4 Channel Margin Actually Goes

A 112G PAM4 link spends its margin long before the SerDes equalizer gets a chance to recover it. The board decides much of the outcome: the stackup, the vias, the BGA breakout, the connector footprint and the AC coupling capacitor pads. In our November 2026 Tech Talk, Fidus Signal Integrity and EMC Architect Dr. Syed Bokhari walked through a medium-reach 112G channel from ASIC to AC capacitor to connector, and showed where that margin goes. This article summarizes the engineering behind it.

Want the full session? Watch the recording on demand.

Why 112G is a different problem from 25G

At 25G NRZ, the line rate is 25.8 Gb/s, the Nyquist frequency is 12.9 GHz and the unit interval is 38.8 ps. At 112G PAM4, the IEEE line rate is 106.25 Gb/s, the Nyquist frequency is 26.6 GHz and the unit interval is 18.8 ps. At 224G PAM4, those become 212.5 Gb/s, 53.1 GHz and 9.4 ps.

PAM4 sends two bits per symbol. That halves the Nyquist frequency compared with NRZ at the same data rate, but the eyes are smaller and the signal-to-noise ratio is worse. NRZ links typically run at a bit error rate better than 1E-12. A 112G PAM4 link runs at a raw BER of about 1E-6 and relies on forward error correction, which adds roughly 6% redundancy.

The “112G” name is a SerDes class, not a line rate. The IEEE rate of 106.25 Gb/s is 100 Gb/s of data plus 256b/257b transcoding and RS(544,514) FEC overhead.

Which metrics actually matter

Insertion loss tells you how much signal reaches the receiver, but on its own it is only informative. The receiver also cares about:

• Insertion loss deviation (ILD): ripple around the fitted insertion-loss curve. Return loss feeds this indirectly.
• Near-end crosstalk (NEXT): a large transmit signal coupling into a small received one. Far-end crosstalk is attenuated along with the signal and matters less.
• Insertion loss to crosstalk ratio (ICR) and P/N skew.

At these rates, IEEE and OIF specifications condense this into Channel Operating Margin (COM) and Effective Return Loss (ERL). COM gives the end-to-end margin with a reference equalizer and needs to be at least 3 dB. ERL limits the reflections that equalization cannot fix.

The via structure comes first

At 112G, you no longer pick a stackup and then fit vias into it. The via structure sets the stackup. These boards typically use HDI with stacked microvias and buried vias, which constrains layer thickness, layer type and prepreg choice.

Material targets from the session:

• Dielectric constant ≤ 3 and loss tangent ≤ 0.002. A lower Dk allows wider traces for the same impedance, which lowers conductor loss and makes the board thinner.
• Low-profile copper. VLP2 (about 2 µm roughness) is common, and VLP3 and VLP4 reduce conductor loss further.
• Spread glass weave and 2-ply prepregs and cores, to reduce fiber weave skew.
• Via-in-pad is a must for BGAs and preferred for AC capacitors and connectors.

Three levels of stacked microvias are routine today. Four and five levels are possible but carry yield risk.

Routing and impedance

Traces are edge-coupled differential pairs, routed on buried layers. A pair pitch of about 12 mils, set by the BGA pitch, and 12 mils between adjacent pairs keeps near- and far-end crosstalk low in the example shown. In that example, insertion loss was about 1.5 dB per inch at 112G, and it roughly doubles at 224G. That figure, more than anything else, limits trace length.

The session also compared 100, 95, 90 and 87 ohm differential pairs. Going below 100 ohm allows wider traces, lower loss and a better match to the vias.

Connector and BGA transitions

The QSFP footprint shows two typical problems.

1. Pad-to-pin stub. Check which way the connector pin bends and place the via on the side that keeps the stub between pad and pin as short as possible. A via on the wrong side turns the whole pad into a stub.
2. Pad capacitance. The pad is much wider than the trace. A rectangular cutout in the adjacent reference plane reduces its capacitance, and a ground via fence improves isolation. Pad compensation typically recovers about 3 dB of return loss. Connector vendors usually provide encrypted 3D HFSS models for this work.

Coaxial connectors perform well up to about 130 GHz, but the trace-to-pad launch still needs 3D optimization and a ground via fence.

The BGA breakout is the largest single discontinuity in the channel. Fidus handles it in four steps: route the escape region, extract it in 3D, simulate differential insertion loss, return loss and TDR, then recommend a launch per layer. With via-in-pad and a shaped pad-to-trace transition, return loss better than -20 dB can be reached up to very high frequencies.

Skew: where CAD tools stop

CAD tools match P/N length on the trace center line, typically to within about 0.5 ps. At high frequencies, current crowds toward the trace edges, so a meandered trace has a slightly shorter effective path and less delay than a straight one. Simulation closes that last gap, and meanders placed near the bumps bring the pair back into phase. Fiber weave skew is always present; rotating the artwork by about 11.25° is a common mitigation.

Prove the link with COM

Once each piece is modeled, the channel is cascaded: package and BGA, PCB trace, AC capacitor, more trace, connector, cable and termination. Cascading S-parameters is an approximation, but a good one when every port sits at the end of a uniform transmission line. The end-to-end S-parameters then go into a COM tool, which reports eye height, vertical eye closure and a pass or fail against COM and ERL.

What the Q&A added

• Are microvias mandatory at 112G? Not strictly. Back-drilled through-hole vias can work, but back-drill tolerance leaves a stub of at least about 6 mils, and its resonance can come close to the frequencies that matter. One or two levels of microvias help and can come free. At 224G, microvias are effectively required.
• Where does the margin go? Usually the transitions, not the trace.
• How accurate are pre-layout loss estimates? About ±15% or more. Copper roughness is the biggest unknown. A test coupon of similar length, measured with a coaxial connector, brings it down to a few percent.
• Will cables or flyover replace the PCB? For long reaches at 224G and above, increasingly. The board still decides the breakout, vias and launch near the package.

Watch the full session

Fidus designs and simulates high-speed boards from stackup through to COM. If you are planning a 112G or 224G board, talk to our signal integrity team.