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Build for AMD Versal® Adaptive SoCs and FPGAs
Power your design from cloud to edge with award-winning expertise.
Unlock performance on Versal™ with
our upcoming joint presentation
Join Fidus and AMD together on March 26th (or register for the on-demand video) – to explore how high-performance DSP algorithms, including MUSIC, can be accelerated using AMD Versal™ AI Engine technology. Watch how to optimize performance, reduce computational load, and enhance signal classification for applications like radar and wireless systems. Register here.
Trusted. Proven. AMD Partner of the Year.
Leverage Fidus’ deep expertise with the AMD Versal family to overcome the challenges of high-tech electronic system design development:
- Advanced Integration: Utilize AMD Versal SoCs’ superior capabilities for adaptive, domain-specific architectures that excel beyond traditional CPUs, GPUs, and FPGAs.
- Streamlined Development: Benefit from our strategic partnership with AMD as North America’s longest Premier Partner. Our up-to-date knowledge of the latest silicon, tools, and software roadmaps drives efficiency.
- Technical Certification: Our large team of AMD-certified professionals (largest in North America) ensure your solutions are implemented swiftly and effectively, significantly shortening time to market.
- Risk Reduction and Acceleration: With Fidus, expect a reduction in development risks and a boost in speed for:
- Developing high-efficiency AI kernels,
- Managing massive data transfers using the Network on Chip (NOC),
- Designing specialized custom hardware.
Our expertise spans the full Versal portfolio
Versal AI Edge Series Gen 2
This series delivers an adaptive technology platform that combines high AI inference performance, low latency, and power efficiency for edge applications. Fidus optimized a Software Defined Radio Design using AI Engines leveraging the AMD VEK280:
- RLS Decision Feedback Equalization
- MLSE Equalization
- Hardware-in-the-loop (MATLAB®)
- Golden vector comparison
Prime Series Gen 2
The mid-range series with medium density programmable logic, signal processing, and connectivity capability.
Fidus developed CXL solutions on Versal featuring:
- CXL engines for Type 1 and Type 3 support
- Verified using UVM, including very Design Systems’ CXL VIP
- Targeted at PCIe Gen5 application
Versal AI Core Series
The high-compute series with medium density programmable logic and connectivity capability coupled with AI and DSP acceleration engines.
Fidus conserved precious logic resources, enhanced design flexibility, and reduced power consumption using the AI Engines in a RADAR application:
- Space Time Adaptive Processing (STAP)
- Custom Kernel development
- Cuboid data movement and processing
- Hardware-in-the-loop (MATLAB®)
- Golden vector comparison
Read more in this whitepaper.
Versal Premium Series
The high-end, high bandwidth series, rich in networking interfaces, security engines, and providing high compute density. Fidus developed robust custom Versal-based hardware for Mil/Aero applications featuring:
- High density compute capabilities
- Rugged 6U VPX Form Factor
- SOSA™ aligned
- Multiple high-speed memory interfaces
- High-speed transceiver links
Versal Technical Webinar Series
Best practices around designing and working with the AMD Versal platform and AI engine.
- Strategies for optimizing FPGA designs with AMD Versal Adaptive SoCs
- Mastering scalable radar signal processing with AMD Versal Devices
- Implementing and Optimizing MIO on AMD Zynq™ UltraScale+™ MPSoC and RFSoC Platforms
Application of AMD Versal Adaptive SoC to Radar Space Time Adaptive Processing (STAP)
In this presentation released in conjunction with AMD, Fidus’ Versal experts discuss the application of AMD Versal Adaptive SoC to Radar Space Time Adaptive Processing (STAP) for detecting moving targets against cluttered backgrounds in space, highlighting the development approach, performance, and advantages of using AMD’s AI engines for this purpose.
Click here to read.
- AIE (AI Engine) implementation and custom Kernel authoring
- Network-on-Chip (NOC)
- DCMAC (100/200/400/600GE)
- SLR (Super Logic Region) restrictions and data transfer
- Proficiency with high performance IO: PCIe Gen4/Gen5/CXL
- HBM memory applications
- Clock and timing
- Complex signal DSP processing
- Thermal simulations
- XPIO interface usage and multiplexing
- MATLAB-based development, verification, coding, targeting, and re-verification
- PCIe Gen4 x16, 64-bit configuration, TLPs (Transaction Layer Packets)
- Vitis™ and Vivado™ experience
- Signal (beyond 112G/PAM4) and Power Integrity (impedance profiling and optimization)
- FPGA and ASIC design and verification
- HBM (High Bandwidth Memory) applications
- Flexibility, performance-based clock and timing subsystems
- Thermal simulations and solutions
- Embedded Software (e.g., Board Support Packages, drivers, etc.)
- Verification (e.g., UVM)
- Complex signal DSP processing
Request a Versal Project Assessment Today!
Get a free architectural risk assessment for your Versal-based project. Our expert team will help you identify strengths, spot risks, and optimize your design.