News


August 10, 2016 – LiVE 88.5 Office Crashers

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OTTAWA, Ontario: The Ottawa office has been crashed! Fidus was a winner of Ottawa’s Alternative Rock Station LiVE 88.5’s Office Crashers contest. Staff endured the balmy 40°C weather and enjoyed a fun-filled lunch hour! Huge thank you to LiVE 88.5 and Jack Astors for the delicious food, music and prizes.

Let it be known that Syed is the reigning office “bucket ball” champion!

August 1, 2016 – Trade Show Exhibit

PHOENIX, Arizona: Scott Turnbull and Michael Wakim demonstrate Fidus’ engineering development kits and services at a Field Application Engineering conference. Also pictured is Don St. Pierre and Brian Mulhearn with partner DesignLinx.

July 25-29, 2016 – Fidus Engineer Awarded at 2016 IEEE International EMC Symposium

OTTAWA, Ontario – Fidus attended the 2016 IEEE International EMC Symposium in Ottawa this past weekend. Dr. Syed Bokhari, SI and EMC Techincal Manager at Fidus, was awarded for outstanding service as the Technical Papers Co-Chair for the 2016 IEEE International Symposium by the IEEE EMC Society. The IEEE EMC Society is the world’s largest organization dedicated to the development and distribution of information, tools and techniques for reducing electromagnetic interference.

Congratulations, Syed!

July 6, 2016 – Fidus Attends Silicon Valley Business Journal’s “The Pitch”

ThePitch_LogoMOUNTAIN VIEW, California – Mike and Tony of Fidus hear a panel discussion about venture capital sentiments at the Silicon Valley Business Journal’s Pitch event, held at the Google Mountain View campus on July 6, 2016. Fidus was invited as a special guest of Technology Credit Union, Fidus’ Silicon Valley banking specialists.

Mike at The Pitch
 

June 29, 2016 – Fidus Attended Silicon Valley Business Journal Seminar

GILROY, California – Michael and Johann Wakim of Fidus enjoyed an evening of networking with Malcolm Bordelon, Market President and Publisher of the Silicon Valley Business Journal after attending the Read to Succeed Seminar earlier that day.

May 26, 2016 – Big Bike Ride for Heart and Stroke Foundation

BigBikeLogo Ride Big. Live Big.Big Bike Tshirt logo

On May 26th, 2016, the Fidus Flyers team set out on a 2km bike ride on the famous 30 seater Big Bike.

Cardiovascular disease is a leading cause of death for Canadian men and women.  And we are very proud of the $2,425.00 Fidus raised for Heart and Stroke Research.

Fidus was one of the top fundraisers in Kanata North contributing to the total $11,479.00 raised in the Kanata North Community.

Fidus dedicated this year’s Big Bike ride to the late Virginie van Ravenswaay.  Our deepest sympathies go out to her family and friends. Her strength, unwavering love and bravery will always remain an inspiration to us all.

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May 6, 2016 – Fidus Attended the Embedded Systems Conference and BIOMEDevice Expo in Boston

ESCFidus attended the  Embedded Systems Conference and BIOMEDevice Expo on May 6th! The Embedded Systems Conference (ESC) is the industry’s largest, most comprehensive technical conference for embedded systems professionals in the US.

The ESC Boston Technical Conference Program consists of 8 tracks covering all aspects of embedded systems design, from concept development through to prototyping, debugging, and manufacturing decisions. ESC is offering a full program of technical training, post-mortems, teardowns, and hands-on sessions, allowing us all to absorb practical, actionable information to cut time, money, and complexity out of the embedded development process.

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The Demo Hall  showcased vendors with new products one could use or evaluate head-to-head for potential future use.

ESC Conference Tracks:

Connected Devices and the IoT | Embedded Software Design | Hardware:

Design, I/O and Interfacing | Prototyping | Embedded Systems Design | Software: Design, Languages, & Quality | Fantastical Theater | Teardowns |


BIOMEDevice_MTW_NE_4cThe BIOMEDevice Expo will be showcasing the latest industry innovations and emerging technologies, including:

Manufacturing Equipment | Cleanroom & Sterilization | Contract Manufacturing | Design Services | Electronic Components | Medical Grade Materials | Packaging & Labeling | 3D Printing | and Testing & QA/QC |

This event includes a 1 day conference on wireless device technology, a full day on quality control and assurance content, 3D printing presentations on both days of the event, and a 75 minute session on medical device design.

There will be dozens of prominent speakers attending, including representatives from Deloitte Consulting, Intel, Medtronic, Philips Healthcare, Smith & Nephew, Stratasys, Stryker, UL and numerous universities.

Both of these events are occurring at the Boston Convention and Exhibition Center.

www.embeddedconf.com/boston/
biomedevice.mddionline.com/

April 18-21, 2016 – Fidus will be attending NAB Show

Hi! I’m Scott Turnbull, Director of Technology at Fidus Systems.

I would like to personally invite you to visit Fidus at the NAB Show, in the Las Vegas Convention Center from April 18th to 21st.

Don’t know Fidus yet? Think of us as your high-speed, high-complexity electronic design services partner that gets your products to market faster.

We’ll be showing off some of our 4K and 8K developments, featuring 12G-SDI, HDMI4K, and Xilinx FPGAs. Get a glimpse of our new 12G-SDI Gearbox, or as we call it, the Gearbox “plus”. Find out why when you stop by.

Use the passcode below for free entry into the exhibits and use Fidus to get your products to market faster.

See you at NAB!

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Details:
Dates: April 18-21, 2016
Location: Las Vegas Convention Center
Booth #: N5520 (North Hall)
Free Exhibits Registration Code: LV4629
Contact: Scott Turnbull (scott.turnbull@fidus.com)

http://nabshow.com/attend/show-overview

How to Correct Interleaving Issues With the Althea 5GSPS FMC Card

Do you ever find yourself running into interleaving issues while using a system with multiple analog-to-digital converters? There can often be differences in gain or phase between the two or multiple channels that are involved with the capture. Fidus and ADI have created a 5GSPS FMC card which works on a multiple analog-to-digital converter that can also correct any unwanted interleaving products. The video above is a live demonstration of how the Althea 5GSPS FMC Card has interleaving correction logic that makes unwanted interleaving spurs disappear.

You can watch how the interleaving spurs appear when the interleaving correction is turned off. The unwanted spurs can be difficult to get rid of so the Althea card proves that it is piece of next generation technology that will be useful for all of your multiple analog-to-digital converters.The Althea 5GSPS 12-bit, JESD204B ADC based FMC is a powerful solution for your prototyping and limited production needs. Visit our products page here for more information about this FMC card, as well as our other FMC and A/D Converters that we offer.

DDR4 Address bus Interconnect Optimization – Syed Bokhari

Abstract— This paper presents an investigation of Signal Integrity of the address bus in a DDR4 memory application. The fly-by topology is simulated at the highest DDR4 switching rate of 1.6 Gbps in a configuration comprising 8 memory devices. Interconnect impedance optimization is carried out to maximize eye opening. A new termination scheme that results in a reduced pattern dependent jitter is described. It consists of the use of series end termination resistors. Numerical results of the effect of trace impedance and termination resistor location are presented.

Presented at the EMC & SI conference, 2015.

Keywords— DDR4, Fly-By topology, series termination, Signal Integrity, Eye diagram, Jitter.

I. INTRODUCTION
DDR4 technology [1] has enabled single ended signaling at data rates as high as 3.2 Gbps. The two main category of buses involved are the data and address, command and control buses. The data bus comprises several byte lanes. Each byte lane includes 8 data bits (termed DQ), a data mask bit (termed DM) at data inversion bit (termed DBI) and a differential strobe (termed DQS). The differential strobe will operate at a frequency of 1.6 GHz. Both the rising and falling edges of the differential DQS bit are used to latch the remaining bits in the byte lane.

The address, command and control bus comprises a differential clock and a number of address, command and control signals. The differential clock operates at a frequency of 1.6 GHz. All address command and control signals are latched only at the rising edge of the clock and consequently their effective rate is 1.6 Gbps.

All signals are connected from a memory controller (Cont.) to each memory device (U1, U2,…). In a single rank memory system, the data bus is a point-to-point bi-directional connection between the memory controller and each memory device. Both the controller and memories have On Die Termination (ODT) and an output impedance that is controllable in discrete steps. Consequently, when a controller is writing data, it can be programmed to use an optimum output impedance and ODT value. This results in a near ideal situation of perfect match enabling extremely high speed data transfer.

Figure 1
Fig 1. Address net topology

The address bus, on the other hand is a multipoint uni-directional connection from a controller to the memory. Therefore, unlike the data bus, the design of this interconnect can be challenging. Signal integrity is ensured by using what is termed a “fly-by” topology with a far end pull-up termination as shown in Fig. 1. The “fly-by” topology is essentially a daisy chain connection with a very short stub. A similar topology is used for the differential clock net as shown in Fig. 2. The eye diagram of the address signal at each memory device must have adequate amplitude and width for an unambiguous detection. It must also be synchronous with respect to the rising edge of the clock signal. The clock signal is required to have an adequate amplitude and a monotonic rising edge. The goal of the interconnect design is to ensure that these requirements are met by a proper choice of interconnect impedance, trace length and termination values.

Figure 2
Figure 2: Clock net topology

First, the case of an interconnect with uniform trace impedance is simulated and is used as the reference. Next, an optimized interconnect impedance case is simulated. In the last two examples, series end-terminators are used to illustrate the benefit. All simulations in this paper use a linear model for the controller with an output impedance of 40 Ohms and a high input impedance model that is typical of memory input pins. PCB thickness is 80 mils and via stub length = 50 mils.

II. COMMON IMPLEMENTATION

A straightforward implementation consists of routing the entire interconnect with a uniform trace impedance of 50 Ohms. Eye diagrams at all the memories are shown in Fig. 3. It can be seen that the waveform integrity is usually the best at the last device closest to the pull up resistor. The first and intermediate devices are more strongly affected by reflections and will exhibit increased jitter and a reduced amplitude.

Figure 3
Fig.3. Case 1: 1.6 Gbps Eye diagrams at the 8 memories (TL1 = 3500 mils, impedance = 50 Ohms, TL2 = TL3 = 1000 mils, impedance = 50 Ohms, STUBS = via with a long stub and a trace length of 100 mils, 50 Ohms trace.

III. INTERCONNECT IMPEDANCE OPTIMIZATION

It is easily possible to optimize by ensuring that stubs and the trace segments TL2-TL3 have high impedance and keeping the impedance of TL1 at a low value. A practical value of low impedance is 25-40 Ohms and high impedance is 50-60 Ohms. Eye diagrams at all the memories are shown in Fig. 4. An improvement in Eye opening, in particular amplitude, is noticeable as compared to Figure 3.

Figure 4
Fig. 4. Case 2: 1.6 Gbps Eye diagrams at the 8 memories (DTL1 = 3500 mils, 40 Ohms impedance, TL2 = TL3 = 1000 mils, 50 Ohms impedance, and , STUBS = via with a long stub and 100 mils of 50 Ohms trace.

IV. OPTIMIZATION USING SERIES END TERMINATIONS

A typical interconnect involving 4 memory devices is shown in Fig. 5 for display clarity. Breakout from the controller and at each memory device requires a via. A short trace segment is also invariably required at each memory pin except in situations where blind vias are used. This constitutes a stub as shown in the inset of Fig. 5. Reflections from each memory device degrade waveform integrity.

Figure 5
Fig. 5. Enlarged view of an address interconnect on PCB
Case 3: 40 Ohms resistance placed at R2
Case 4: 40 Ohms resistance placed at R1

Reflections in transmission lines can be reduced or eliminated by using passive termination elements [2]. Commonly used terminations consist of series resistors placed close to the source, and shunt terminations placed close to a receiver. In this work, the use of a series resistance placed close to a receiver is investigated. Basically a resistance of a value equal to the transmission line impedance will combine with input capacitance of the receiver and act as an RC termination reducing high frequency reflections.

Therefore, if a discrete resistance can be placed at the precise location of the stub, namely R1 (hypothetical), one would expect an attenuation of the reflected signal. Alternatively the resistor can also be placed at R2 which is more realistic. Simulated results for both locations for the resistance of a value = 40 Ohms are tabulated in Table I. The waveforms for Case 3 only are shown in Fig. 6. Those for Case 4 cannot be visibly distinguished and are omitted.

It can be seen that the use of resistive end termination is most effective at the position R1. Placement at the position R2 will also yield an improvement in the eye opening although with a slightly reduced performance. Both cases show a substantial reduction in jitter. The value of the termination resistance also plays an important role. If the value is too large, amplitude reduces and affects noise margin adversely although there will be a reduction in jitter. If the value is too small, both jitter and amplitude increase. A value in 40-50 Ohms range is found to be best suited.

It is also of importance to determine the effect of end terminators on the clock waveform. In simulations, the topology of the clock net is identical to that of the address net and trace lengths are also identical, i.e., DTL1 = TL1, DTL2 = TL2, and DTL3 = TL3, and DSTUB = STUB in Figures 1-2. This is required to ensure synchronism between the clock and address net. The differential transmission lines are treated as two single ended uncoupled lines. The differential impedance of DTL1-3 and DSTUB is simply twice that of TL1-3 and STUB. Figures 7 and 8 show one cycle of the differential clock waveform for cases 2 and 3. Other cycles are suppressed for clarity. It can be seen that the waveform amplitude is more attenuated at the last memory device for case 3 although the requirements are still met.

Lastly, the impact of optimization on the relative delay between clock and data nets is analyzed. Figure 9 shows the strep response of both clock and data nets for case 2. It can be seen that the clock is delayed with respect to the address net and the delay increases as one moves away from the controller. In this case the delay difference is 106-12 = 94 pS.

Figure 10 shows the step response of both clock and data nets for case 3. It can be seen that the clock is delayed more due to the resistive loading. In this case the delay difference is 120-32 = 88 pS, which is less than that of case 2.

In both cases, the clock can centered by making DTL1 to be ~50 pS longer than TL1. There is no significant signal integrity benefit in using series end terminations on the clock net although it would certainly help in reducing radiation.

 

TABLE I. EYEOPENING FOR THE CASES SIMULATED

 

Table 1

 

Figure 6
Fig. 6. Case 3: 1.6 Gbps Eye diagrams at the 8 memories (TL1 = 3500 mils, 40 Ohms impedance, TL2 = TL3 = 1000 mils, 50 Ohms impedance, and , STUBS = via with a long stub and 100 mils of 50 Ohms trace, 40 Ohms series end termination resistors placed at position R2 at each memory device.

Figure 7
Fig. 7. Differential Clock waveforms for case 2

Figure 8
Fig. 8. Differential Clock waveforms for case 3

Figure 9
Fig. 9 Step response of clock and address net for Case 2. (Address waveform offset by 1 V for clarity)

Figure 10
Fig.10. Step response of clock and address net for Case 3 (Address waveform offset by 1 V for clarity)

V. CONCLUSION

In this work, signal integrity of the address bus in a DDR4 memory system is investigated. It is shown that jitter can be reduced by using series end terminators at the memory devices. Implementation of such a scheme using discrete resistors would become impractical due to space constraints. This can be circumvented with the use embedded passive resistors. The termination technique is also useful in other applications involving multi-point buses. In particular, it can ensure monotonic clock edges, and also help in reducing radiation without compromising waveform integrity significantly.
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Syed Bokhari of Fidus Systems
REFERENCES

[1] DDR4 SDRAM Standard, JEDEC JESD 79-4, September 2012. [2] Brian Young, Digital Signal Integrity, New Jersey: Prentice Hall, 2001, Chapter 2.