Fidus Solution Portfolio

This reference design targets the 5G NR millimeter wave wireless network leveraging  mmWave Phased Array Antennas for Broadband Connectivity. The reference design was done on an AMD/Xilinx platform to support and enable eCPRI | MAC | Optics.

Participated in a Communication Payload Design for LEO Satellite Systems, leveraging Fidus Software Engineers

We collaborated with a telecommunications client to design an O-RAN Fronthaul Gateway using Intel® Stratix® 10 architectural silicon. The solution enabled seamless translation between CPRI and ORAN protocols on a Line Card Distributed Unit (DU), supporting 25Gbps Ethernet streams and 18 channels of 10Gbps CPRI interfaces. Our involvement covered IP development, integration, and verification support, ensuring accelerated deployment timelines.

We designed a custom FMC+ (VITA 57.4) to CFP2 adapter card leveraging Intel® Agilex™ architectural silicon to enable the expansion of an existing development board to a CFP2 connector. The design supported 8 lanes of TX and 8 lanes of RX, operating at speeds up to 58Gbps using PAM4 signaling. Delivered within an accelerated 8-week timeframe, we showcased expertise in high-speed hardware design, precision PCB layout, and advanced signal integrity simulation, ensuring seamless integration and rapid prototyping success.

Fidus partnered with an aerospace and defense client. to support the development and testing of software for satellite hardware, specifically for a Low Earth Orbit (LEO) satellite payload. The project involved consolidating multiple initiatives into one, with the primary focus on board bring-up, script development, and testing of an AMD Zynq UltraScale+ MPSoC-based system. Fidus played a key role in developing Python-based test scripts, which were initially executed without hardware and later validated on real equipment.

The project also included exploring and supporting the client’s Yocto approach for secure communication and upgrades. Fidus ensured secure data transmission between the satellite and ground station, using encryption techniques for data captured by the satellite’s camera, control messages, and software upgrades. Key technologies such as Spacewire for transport, D-Bus for message exchange, and protobuf for communication serialization were used throughout the system. The development process was managed using the client’s GitLab repository with secure USB hardware keys.

A client requested Fidus to integrate their proprietary technology into a unique product. Fidus was responsible for the full development, including electronic hardware design, FPGA coding, mechanical and thermal design, and embedded software architecture. Using a Xilinx Zynq Ultrascale+ MPSoC, the project included signal conditioning, clock recovery, FMC interface, signal conversion, optical QSFP communications, and PRBS-based error detection.

The embedded application ran on Linux hosted on the quad-core Arm Cortex-A53. Deliverables included bootloader/BSP, IP over PPP, support for various USB peripherals, and data gathering from a Cortex-M4 for ADC and sensor information. We provided a Yocto build environment and Jenkins automation for future builds. The project concluded on time, within budget, and with a cohesive embedded software solution.

This main control card is used in a pole-mount system that provides wireless access and backhaul functionality. Being an outdoor, pole-mount application, conductive cooling, and wide temperature operation were critical design factors. An onboard Intel® PowerPC® processor supervises a multi-port L2+ DRAM-enabled switching structure. Additionally, there is a robust, seamless switching power circuit to provide battery back-up and charging and lightning protection circuitry to help ensure reliable operation.

This system was designed for a semiconductor manufacturer who needed both a reference design for their customers, as well as an experimentation platform for their new central office VDSL chipset. The reference portion of the design was limited to 4-layers and was specifically designed with commonly available components. The control plane of the design contained two ARM® processors, and a mail boxing system. As per CO requirements, the system was -48V powered.

This involved design was made by designing and connecting four unique circuit card assemblies, and a large pole-mount conduction cooled chassis. The complex electronics relied on several AMD/Xilinx® FPGAs, a Freescale® processor, multiple -48V isolated converters, a great deal of analog circuitry, including ADCs and DACs, RF circuitry (2.5 and 3.5GHz), and high-speed serial links.

One of the most elegant solutions within this design was the RF connection block that allowed multiple SMP RF connectors to blind mate directly to the antenna array.

This full turnkey project involved all our disciplines: Hardware, FPGA, Layout, Embedded Software, Signal Integrity, and Mechanical. We brought in special dedicated test sets to verify operation and assess critical performance parameters such as EVM. We had custom cavity filters manufactured to achieve the performance goals.