Fidus Solution Portfolio

We worked with an aerospace leader to provide embedded software design and FPGA engineering support for a custom space technology development platform based on AMD/Xilinx® ZU5EV architectural silicon. Our team optimized DDR4, USB3, and Ethernet communication protocols while reviewing and refining existing Vivado projects. The collaboration extended into a multi-phase engagement, ensuring seamless firmware upgrades and FPGA performance validation.

This reference design targets the 5G NR millimeter wave wireless network leveraging  mmWave Phased Array Antennas for Broadband Connectivity. The reference design was done on an AMD/Xilinx platform to support and enable eCPRI | MAC | Optics.

This prototype was developed as an FPGA-based signal processing platform that will be used to emulate some of the Client’s desired ASIC functions.

This Emulation System relied on the AMD ZCU208 RFSoC Evaluation Platform and a minimal software set which will boot PetaLinux and provide register access to Fidus determined FPGA parameters. It also allows the configuration of the onboard clocking subsystem.

Participated in a Communication Payload Design for LEO Satellite Systems, leveraging Fidus Software Engineers

Fidus partnered with the search and rescue division of a global aerospace and defense company to enhance their software suite, designed to decode emergency beacons and communicate with the appropriate authorities. The software runs on Windows Servers and is built using Java, C++, SQL Server, and MongoDB. Fidus worked closely with global teams split between Ottawa and India, to resolve issues in the first-generation product and set the foundation for the development of the second-generation system.

Fidus contributed to fixing critical bugs and participated in daily scrum meetings to address enhancements and feedback. The project also focused on potentially upgrading the software’s UI to support MongoDB for an additional client, as well as improving the existing testing and integration processes.

Fidus partnered with an aerospace and defense client. to support the development and testing of software for satellite hardware, specifically for a Low Earth Orbit (LEO) satellite payload. The project involved consolidating multiple initiatives into one, with the primary focus on board bring-up, script development, and testing of an AMD Zynq UltraScale+ MPSoC-based system. Fidus played a key role in developing Python-based test scripts, which were initially executed without hardware and later validated on real equipment.

The project also included exploring and supporting the client’s Yocto approach for secure communication and upgrades. Fidus ensured secure data transmission between the satellite and ground station, using encryption techniques for data captured by the satellite’s camera, control messages, and software upgrades. Key technologies such as Spacewire for transport, D-Bus for message exchange, and protobuf for communication serialization were used throughout the system. The development process was managed using the client’s GitLab repository with secure USB hardware keys.

Fidus worked with a transportation client to replace hardware components with software equivalents, creating an emulation system for a control platform. The solution emulated fault conditions, errors, and various test vectors, allowing for flexible and scalable testing. The project utilized C++ in a Linux environment on an x86 platform, while integrating DDS for real-time messaging.

Fidus also developed a custom tool to identify changes between system loads, enhancing the client’s QA processes. Throughout the project, we guided this client through multiple iterations of scope and requirements to ensure alignment among stakeholders.

This project highlights Fidus’ expertise in x86 environments and software emulation, as well as our extensive experience with AMD Zynq UltraScale+ MPSoC platforms, allowing us to offer highly flexible solutions for industrial control systems.

A client requested Fidus to integrate their proprietary technology into a unique product. Fidus was responsible for the full development, including electronic hardware design, FPGA coding, mechanical and thermal design, and embedded software architecture. Using a Xilinx Zynq Ultrascale+ MPSoC, the project included signal conditioning, clock recovery, FMC interface, signal conversion, optical QSFP communications, and PRBS-based error detection.

The embedded application ran on Linux hosted on the quad-core Arm Cortex-A53. Deliverables included bootloader/BSP, IP over PPP, support for various USB peripherals, and data gathering from a Cortex-M4 for ADC and sensor information. We provided a Yocto build environment and Jenkins automation for future builds. The project concluded on time, within budget, and with a cohesive embedded software solution.

We took a AMD/Xilinx® ML605 development kit, an Avnet® HDMI FMC card, and a Panasonic® 1080p60 streaming camera, and made a video demo. The demo is set-up by recording four independent hi-def feeds into the onboard DDR3 memory. We then placed all four videos on the screen at one time, so before we store them into memory, we scale the feeds, and then dump them into memory. Next, we start the camera streaming live video. This live video is scaled, and overlayed onto the four simultaneous video playbacks. Building on this, we also decided to smoothly move the live video feed around the screen, rebounding as it comes to the edge of the display; all at full high definition 1080p60 rates.

This system consists of a AMD/Xilinx® MicroBlaze® soft core, a DDR3 memory controller, and a whole bunch of custom scaling, overlay, video processing, and movement code.

This solution has since been ported to the AMD/Xilinx® KC705 development kit.

The design utilized a DVI-D connector as well as a DVI-I connector. The DVI connectors were the connections to the outside world and directed data into and out of an FPGA. Both sides relied on a TMDS transceiver, and the analog portion of the DVI-I was accomplished using a Dual DAC. The FPGA was responsible for processing both the high-speed video data as well as the DDC (I²C) bus.