Fidus Solution Portfolio

Fidus partnered with an aerospace and defense client. to support the development and testing of software for satellite hardware, specifically for a Low Earth Orbit (LEO) satellite payload. The project involved consolidating multiple initiatives into one, with the primary focus on board bring-up, script development, and testing of an AMD Zynq UltraScale+ MPSoC-based system. Fidus played a key role in developing Python-based test scripts, which were initially executed without hardware and later validated on real equipment.

The project also included exploring and supporting the client’s Yocto approach for secure communication and upgrades. Fidus ensured secure data transmission between the satellite and ground station, using encryption techniques for data captured by the satellite’s camera, control messages, and software upgrades. Key technologies such as Spacewire for transport, D-Bus for message exchange, and protobuf for communication serialization were used throughout the system. The development process was managed using the client’s GitLab repository with secure USB hardware keys.

Fidus worked with a transportation client to replace hardware components with software equivalents, creating an emulation system for a control platform. The solution emulated fault conditions, errors, and various test vectors, allowing for flexible and scalable testing. The project utilized C++ in a Linux environment on an x86 platform, while integrating DDS for real-time messaging.

Fidus also developed a custom tool to identify changes between system loads, enhancing the client’s QA processes. Throughout the project, we guided this client through multiple iterations of scope and requirements to ensure alignment among stakeholders.

This project highlights Fidus’ expertise in x86 environments and software emulation, as well as our extensive experience with AMD Zynq UltraScale+ MPSoC platforms, allowing us to offer highly flexible solutions for industrial control systems.

A client requested Fidus to integrate their proprietary technology into a unique product. Fidus was responsible for the full development, including electronic hardware design, FPGA coding, mechanical and thermal design, and embedded software architecture. Using a Xilinx Zynq Ultrascale+ MPSoC, the project included signal conditioning, clock recovery, FMC interface, signal conversion, optical QSFP communications, and PRBS-based error detection.

The embedded application ran on Linux hosted on the quad-core Arm Cortex-A53. Deliverables included bootloader/BSP, IP over PPP, support for various USB peripherals, and data gathering from a Cortex-M4 for ADC and sensor information. We provided a Yocto build environment and Jenkins automation for future builds. The project concluded on time, within budget, and with a cohesive embedded software solution.

We took a AMD/Xilinx® ML605 development kit, an Avnet® HDMI FMC card, and a Panasonic® 1080p60 streaming camera, and made a video demo. The demo is set-up by recording four independent hi-def feeds into the onboard DDR3 memory. We then placed all four videos on the screen at one time, so before we store them into memory, we scale the feeds, and then dump them into memory. Next, we start the camera streaming live video. This live video is scaled, and overlayed onto the four simultaneous video playbacks. Building on this, we also decided to smoothly move the live video feed around the screen, rebounding as it comes to the edge of the display; all at full high definition 1080p60 rates.

This system consists of a AMD/Xilinx® MicroBlaze® soft core, a DDR3 memory controller, and a whole bunch of custom scaling, overlay, video processing, and movement code.

This solution has since been ported to the AMD/Xilinx® KC705 development kit.

The design utilized a DVI-D connector as well as a DVI-I connector. The DVI connectors were the connections to the outside world and directed data into and out of an FPGA. Both sides relied on a TMDS transceiver, and the analog portion of the DVI-I was accomplished using a Dual DAC. The FPGA was responsible for processing both the high-speed video data as well as the DDC (I²C) bus.

The semiconductor manufacturer asked us to design a board that they could use to both validate functionality as well as characterize operation by placing a thermal hood over their IC. This board allowed our customer to validate I/O operation, internal register operation, and characterize their IC across temperature.

In this type of development, we minimize the support circuitry so that we can minimize project cost, schedule, and risk. This includes utilizing off-the-shelf system on modules (SOMs; in this case a RabbitCore®) in conjunction with simple GUIs, to control the ASIC.

We designed this ASIC emulation board so our customer could validate their RTL prior to committing to ASIC. Built around three AMD/Xilinx® Virtex-II PRO® FPGAs (the largest FPGAs in the world at the time), this board met all input/output requirements of the final ASIC, but also included the complexity associated with the multiple high-speed parallel links that allowed the FPGAs to communicate with each other. Note: This could now be done in a single AMD/Xilinx® Virtex-7® 2000T.

A multi-industry design intended to allow customers to evaluate and develop with AMD/Xilinx® Zynq™. Relying on our AMD Premier member status, we completed this design prior to the general availability of Zynq™, making this one of the first Zynq™ solutions ever created. This early adoption is a hallmark of Fidus’ technology-first attitude, and ensures that we can offer extremely early expertise in the latest pivotal technologies.

This robust, conduction cooled HPC FMC card was designed to interface to a large variety of host cards. It provides multiple ADC channel inputs, clock generation and low jitter distribution, power regulation and post filtering. Utilizing our lab equipment, the analog front-end was parameterized and characterized. This product passes high-speed serial data to the FPGA host card utilizing JEDEC’s JESD204B serial standard for data converters; the Xilinx® JESD204B IP core was utilized.

Having already developed an Automatic Identification System airborne receiver, we set out to design a compact AIS Class B Transponder for international maritime operation. Our AIS B solution utilized a AMD/Xilinx® Spartan-6® based software defined radio resulting in extremely clean transmit bursts, and an extremely sensitive AIS receiver. We wrote the AIS protocol stack to run on the onboard ARM processor. A vast number of different I/O options were supported. This system is a great example of Fidus delivering complex hardware, RF, FPGA, embedded software, and mechanical design- a real turnkey project.

This product was independently tested and complied with the international AIS protocol and RF performance requirements.