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Webinar – Thursday July 22nd @ 12:00PM (EST)

7 July 2021


Debugging High Speed SERDES issues in Multi-board Interconnect systems.


July 22 2021 @ 12:00 – 12:45 Eastern




High-speed signal integrity (SI) has many complex challenges with the doubling of signal speeds every generation. This presentation will focus on how to debug SERDES in interconnected systems. Most common as well as complicated mechanisms that cause increased BER will be covered with practical examples.


Anyone interested in understanding more about Signal Integrity with a focus on SERDES. An electrical engineering background is recommended as we get right into the details during this webinar.


Dr. Syed. A. Bokhari has worked with Fidus for over 19 years. He received the BE degree in Electronics Engineering from the Visveswaraya College of Engineering of Bangalore University in 1980, The M.Sc.(Eng.) degree in Electrical Communication Engineering from the Indian Institute of Science (IISc), Bangalore, India in 1982 and the Ph.D. degree from the Department of Aerospace Engineering, IISc in 1986. He is currently a Signal Integrity Architect at Fidus Systems Inc., Ottawa, Canada. Prior to this, he has held positions of Senior Member of Consulting Staff at Cadence Design Systems (Canada) Ltd., and Research Associate at the Laboratory of Electromagnetism and Acoustics of the Swiss Federal Institute of Technology in Lausanne, Switzerland. He was the Technical Papers Co-Chair of the 2016 IEEE EMC Symposium in Ottawa and is the chairman of the IEEE Ottawa EMC Chapter. He received the Outstanding Paper Award in Signal Integrity at EDICON 2017 in Boston. His areas of research interests include Printed Circuit Board design for Signal and Power Integrity, and EMC, Numerical Methods in Electromagnetics, and Miniaturized Antennas. He has many publications in these areas and holds two patents.

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