Project Description

8-Channel, 250MSPS, JESD204B ADC FMC

  • Achieved datasheet specified performance
  • Low noise mixed signal design
  • Demonstrates JESD204B interface
  • Low jitter clock generation and distribution
  • FMC (VITA 57.1) compatibilitiy
  • Fully characterized with VNA
  • Xilinx FPGA targeted