Project Description

5GSPS, 12-bit, ADC, JESD204B FMC

  • 5GSPS operation achieved by interleaving two 2.5GSPS ADCs
  • Analog input, trigger input, and clock input
  • RF-like clock distribution for extremely low jitter sampling
  • Innovative clock phase adjustment system
  • FPGA-based reference DSP design to compensate for interleaving-related spectral content
  • Double width FMC (VITA 57.1) design

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