Abstract — Serial communication links have become indispensable in data transfer, primarily in chip to chip communications over printed circuit boards and backplanes. Data rates of 10 Gbps are common today and rates as high as 25 Gbps are feasible. Use of advanced signal processing techniques in SERDES (Serializers/Deserializers) such as transmit pre-emphasis and receive equalization have enabled reliable operation of these links on channels that can be severely impaired. Yet, fundamental limitations remain and certain shortcomings in channel characteristics cannot be corrected. Therefore, it is important to pay close attention to the Printed Circuit Board (PCB) layout to ensure robust error free transmission of high speed serial data. This paper presents a description of factors that affect link performance and methods for controlling them at the PCB level.
To be presented at the IEEE MTT-S International Conference On Numerical Electromagnetic and Multiphysics Modeling and Optimization in August 2015
Key Words — SERDES, Serial Links, IEEE 10G Base KR, Interlaken, Pre-Emphasis, Equalization
In general, a serial link comprises a transmit module, a receive module, and everything in between termed a “channel”. In networking and telecommunications equipment, the channel usually comprises line cards and a backplane or a mid-plane. Assuming linearity, the waveform at the receiver is simply a convolution of the transmit waveform with the impulse response of the channel. If the channel frequency response is uniform as a function of frequency, the received wave shape would be identical to that of the transmitted wave. In reality however, all channels have frequency dependent characteristics and as a result the received waveform can undergo considerable distortion. Further, noise from an adjacent channel, a neighboring signal, or power supply is always present affecting waveform integrity.
Channel characteristics adversely affect received signal eye amplitude and width. This is due to pattern dependent jitter in the case of data signals and jitter amplification in the case of clock signals. The receiver requires certain minimum signal amplitude usually in rage of 100mV peak to peak and a certain minimum pulse width, usually a small fraction UI (Unit Interval) to reliably distinguish a “one” data bit from a “zero” data bit. These numbers determine the Bit Error Rate (BER) and serve the purpose of defining an “Eye Mask”. Eye masks provide a convenient and unique metric for quantifying performance and have been recommended by many standards. Alternatively, link performance can also be quantified in a relative manner by a specification of the frequency domain characteristics. These include a number of variables that are derived from the s-parameters of the channel namely, Insertion Loss (IL), Return Loss (RL), Skew, Insertion Loss Deviation (ILD) and Insertion Loss to Cross Talk Ratio (ICR). They are commonly specified as additional requirements in newer standards. The goal of channel design is therefore to ensure that the frequency response of the channel meets requirements on the s-parameters of the particular standard.
Channel behavior can be represented by s-parameters in a complex manner. This requires simulations using three dimensional Electromagnetic field solvers or a precision measurement via Vector Network Analyzers. In this paper, numerical illustrations will be provided to give designers an idea and an indication of a “rough order of magnitude”. The precise physical and electrical detail of geometries analyzed is therefore intentionally omitted. In all simulations to follow, except where explicitly mentioned, the PCB material is assumed to be in the “mid-range” as defined later, the line card is 115 mils thick with 24 layers, and the backplane is 200 mils thick with 20 layers. Copper weight of traces is half ounce. PCB trace widths, drill and pad diameters are nominal values for PCBs of the thickness selected.
II. Channel Modeling Using S-Parameters
We will illustrate a typical design using a back plane example. Assume that the task is to design a 10 Gbps serial link on a backplane and a line card containing a Transmitter (TX) and a Receiver (RX) device. First, an interconnect budget needs to be established. For the commonly used form of binary signaling, the Nyquist frequency in GHz (fnyq) is one half of the maximum data rate in Gbps.
For a data rate of 10 Gbps, the Nyquist frequency is 5 GHz and the UI is 100 pS. Most transceivers have built in transmit pre-emphasis, amplification and receive equalization and can handle a total link insertion loss of 25 dB or more at the Nyquist frequency. This provides a constraint on the maximum insertion loss and the need to have a retimer/repeater or not is established. For this illustration, it is assumed that the physical dimensions of the backplane and line cards permit operation without retimers/repeaters.
Next, the available insertion loss of ~25 dB is distributed over all the elements of the link. In the case of a backplane system, one may allow line cards to have an insertion loss of say up to 4 dB, and reserve 10 dB for the backplane alone as shown in Table 1. Other elements of the link include the chip package, the AC coupling capacitor and the connectors. The values of insertion loss shown are typical for these components at 5 GHz. A margin is always desirable to allow for uncertainties in PCB trace insertion loss. A value of 2 dB or more is considered adequate.
Channel physical properties have a direct effect on the s-parameters. The received eye width and height is influenced by the following channel s-parameter characteristics some of which are well known (Fig. 1). The last 2 are defined by the IEEE for example in reference :
Differential channel Insertion Loss (IL): This is simply the loss of signal power arising from the insertion of the channel. Losses occur due to reflection, absorption and radiation and all of them contribute to the insertion loss.
Return Loss (RL): This is the loss of signal power arising from reflections only and is caused by impedance discontinuities in the channel. Differential return loss takes precedence although some standards also specify a common mode return loss.
Skew between P and N members of a differential pair: This is the time delay between the P and N portions of a differential interconnect. This can arise due to a physical difference in the path length or the velocity of propagation of the two parts P and N.
Insertion Loss Deviation (ILD): The IL of a lossy transmission line increases with frequency in a logarithmic fashion. Deviations of this straight line behavior (on a log scale) occur due to impedance mismatch and other factors. It is important to limit such deviations. ILD is defined as the maximum deviation of IL from the best fit attenuation vs. frequency characteristic.
Insertion Loss to Crosstalk Ratio (ICR): This is the ratio of IL to the total crosstalk at the receiver. Total cross talk is computed by taking the power sum of the coupled differential s-parameter values, namely FEXT (Far End Cross Talk) and NEXT (Near End Cross Talk) values from all aggressors.
Some standards will specify Channel Operation Margin (which is a simple limiting budgeting allocation on all the above parameters as shown in Fig. 1. In addition to this, limits on the trace differential impedance, differential-to-common mode s-parameters, or an Eye Mask may also be defined. It is important to remember that meeting these requirements increases the confidence level of successful link operation. Failure to meet them simply increases risk, introduces uncertainty in operation and an increased Bit Error Ratio (BER). A graceful degradation in performance, such as a need to operate at a lower data rate is more likely than a complete catastrophic failure.
III. Channel Physical Properties
Channel physical properties shown in Figure 2 have a direct impact on the s-parameters and the Eye diagram. PCB traces category includes (1) trace type which affects IL, (2) Trace Impedance which affects ILD and RL, (3) Trace coupling which affects IL, RL and ILD, (4) Trace thickness and surface roughness which affects IL, (5) Trace coating which affects IL, RL and Skew, (6) Trace bends which affect IL and Skew, (7) Trace spacing which affects ICR, (8) Trace reference planes which affects ILD, and the use of Trace coupons. PCB material affects IL and Skew. PCB vias affect RL, ILD and ICR. AC coupling capacitors affect IL, ILD and RL. The PCB stackup, connectors and BGA breakout affect all 5 parameters. Details of their influence will be presented with numerical examples where possible.
IV. Numerical Illustration and Conclusion
An illustration of the application is shown in Fig. 3 for a mid-plane system. The serial link traverses an orthogonal connector and the s-parameters of the link are shown in Fig. 4. The transmit and receive devices have output power control, pre-emphasis, amplification and adaptive equalization. Simulated Eye diagram with optimized device settings for 25 Gbps operation is shown in Fig. 5 and the eye opening has adequate margin for an error free operation. Design detail will be presented.
Syed Bokhari of Fidus Systems
 IEEE Std. 802.3ap™-2007 Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, Amendment 4: Ethernet Operation over Electrical Backplanes Approved 22 March 2007, IEEE-SA Standards Board (Amendment to IEEE Std 802.3™-2005)