Description: This robust, conduction cooled HPC FMC card was designed to interface to a large variety of host cards. It provides multiple ADC channel inputs, clock generation and low jitter distribution, power regulation and post filtering. Utilizing our lab equipment the analog front-end was parameterized and characterized. By the way, it passes high-speed serial data to the FPGA host card utilizing JEDEC’s JESD204B serial standard for data converters; the Xilinx® JESD204B IP core was utilized.

Technologies: ADC, analog-to-digital conversion, low jitter, clock generation, clock distribution, JESD204B, VITA 57.1, linear regulation, LDO, SSMC, balun, transformer, differential pairs, matching, network analyzer, spectrum analyzer, Xilinx® ChipScope, Xilinx® ILA

Layers: 12

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