March 10 – Fidus Achieves Top 100 Small & Medium Canadian Employer for 2015

Canada’s Top Small & Medium Employers

March 10, 2015

Fidus Systems Inc. has been awarded as one of Canada’s Top Small and Medium Employers. The announcement was made this morning, highlighting 100 of Canada’s most innovative SMEs.

“Fidus is an exciting and attractive place to work. This award is a reflection of the challenging work we provide, the closeness of our team, and the focus on our 8 Guiding Principles. We are very proud to be recognized as one of Canada’s Top SMEs,” says Fidus CEO, Michael Wakim.

Canada’s Top Small & Medium Employers gives recognition to companies which stand out in their originality in the workplace. SMEs contribute 50% of the country’s GDP, and close to 90% of the private-sector workforce.

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Fidus Press Release

Signal Integrity Considerations for the PCB implementation Of Multi-Gigabit SERDES Links – Syed Bokhari

Abstract — Serial communication links have become indispensable in data transfer, primarily in chip to chip communications over printed circuit boards and backplanes. Data rates of 10 Gbps are common today and rates as high as 25 Gbps are feasible. Use of advanced signal processing techniques in SERDES (Serializers/Deserializers) such as transmit pre-emphasis and receive equalization have enabled reliable operation of these links on channels that can be severely impaired. Yet, fundamental limitations remain and certain shortcomings in channel characteristics cannot be corrected. Therefore, it is important to pay close attention to the Printed Circuit Board (PCB) layout to ensure robust error free transmission of high speed serial data. This paper presents a description of factors that affect link performance and methods for controlling them at the PCB level.

To be presented at the IEEE MTT-S International Conference On Numerical Electromagnetic and Multiphysics Modeling and Optimization in August 2015

Key Words — SERDES, Serial Links, IEEE 10G Base KR, Interlaken, Pre-Emphasis, Equalization

I. Introduction
In general, a serial link comprises a transmit module, a receive module, and everything in between termed a “channel”. In networking and telecommunications equipment, the channel usually comprises line cards and a backplane or a mid-plane. Assuming linearity, the waveform at the receiver is simply a convolution of the transmit waveform with the impulse response of the channel. If the channel frequency response is uniform as a function of frequency, the received wave shape would be identical to that of the transmitted wave. In reality however, all channels have frequency dependent characteristics and as a result the received waveform can undergo considerable distortion. Further, noise from an adjacent channel, a neighboring signal, or power supply is always present affecting waveform integrity.

Channel characteristics adversely affect received signal eye amplitude and width. This is due to pattern dependent jitter in the case of data signals and jitter amplification in the case of clock signals. The receiver requires certain minimum signal amplitude usually in rage of 100mV peak to peak and a certain minimum pulse width, usually a small fraction UI (Unit Interval) to reliably distinguish a “one” data bit from a “zero” data bit. These numbers determine the Bit Error Rate (BER) and serve the purpose of defining an “Eye Mask”. Eye masks provide a convenient and unique metric for quantifying performance and have been recommended by many standards. Alternatively, link performance can also be quantified in a relative manner by a specification of the frequency domain characteristics. These include a number of variables that are derived from the s-parameters of the channel namely, Insertion Loss (IL), Return Loss (RL), Skew, Insertion Loss Deviation (ILD) and Insertion Loss to Cross Talk Ratio (ICR). They are commonly specified as additional requirements in newer standards. The goal of channel design is therefore to ensure that the frequency response of the channel meets requirements on the s-parameters of the particular standard.

Channel behavior can be represented by s-parameters in a complex manner. This requires simulations using three dimensional Electromagnetic field solvers or a precision measurement via Vector Network Analyzers. In this paper, numerical illustrations will be provided to give designers an idea and an indication of a “rough order of magnitude”. The precise physical and electrical detail of geometries analyzed is therefore intentionally omitted. In all simulations to follow, except where explicitly mentioned, the PCB material is assumed to be in the “mid-range” as defined later, the line card is 115 mils thick with 24 layers, and the backplane is 200 mils thick with 20 layers. Copper weight of traces is half ounce. PCB trace widths, drill and pad diameters are nominal values for PCBs of the thickness selected.

II. Channel Modeling Using S-Parameters

We will illustrate a typical design using a back plane example. Assume that the task is to design a 10 Gbps serial link on a backplane and a line card containing a Transmitter (TX) and a Receiver (RX) device. First, an interconnect budget needs to be established. For the commonly used form of binary signaling, the Nyquist frequency in GHz (fnyq) is one half of the maximum data rate in Gbps.

Syed - 1
TABLE I – Link Insertion Loss Budget

For a data rate of 10 Gbps, the Nyquist frequency is 5 GHz and the UI is 100 pS. Most transceivers have built in transmit pre-emphasis, amplification and receive equalization and can handle a total link insertion loss of 25 dB or more at the Nyquist frequency. This provides a constraint on the maximum insertion loss and the need to have a retimer/repeater or not is established. For this illustration, it is assumed that the physical dimensions of the backplane and line cards permit operation without retimers/repeaters.

Next, the available insertion loss of ~25 dB is distributed over all the elements of the link. In the case of a backplane system, one may allow line cards to have an insertion loss of say up to 4 dB, and reserve 10 dB for the backplane alone as shown in Table 1. Other elements of the link include the chip package, the AC coupling capacitor and the connectors. The values of insertion loss shown are typical for these components at 5 GHz. A margin is always desirable to allow for uncertainties in PCB trace insertion loss. A value of 2 dB or more is considered adequate.

Channel physical properties have a direct effect on the s-parameters. The received eye width and height is influenced by the following channel s-parameter characteristics some of which are well known (Fig. 1). The last 2 are defined by the IEEE for example in reference [1]:

Differential channel Insertion Loss (IL): This is simply the loss of signal power arising from the insertion of the channel. Losses occur due to reflection, absorption and radiation and all of them contribute to the insertion loss.
Return Loss (RL): This is the loss of signal power arising from reflections only and is caused by impedance discontinuities in the channel. Differential return loss takes precedence although some standards also specify a common mode return loss.
Skew between P and N members of a differential pair: This is the time delay between the P and N portions of a differential interconnect. This can arise due to a physical difference in the path length or the velocity of propagation of the two parts P and N.
Insertion Loss Deviation (ILD): The IL of a lossy transmission line increases with frequency in a logarithmic fashion. Deviations of this straight line behavior (on a log scale) occur due to impedance mismatch and other factors. It is important to limit such deviations. ILD is defined as the maximum deviation of IL from the best fit attenuation vs. frequency characteristic.
Insertion Loss to Crosstalk Ratio (ICR): This is the ratio of IL to the total crosstalk at the receiver. Total cross talk is computed by taking the power sum of the coupled differential s-parameter values, namely FEXT (Far End Cross Talk) and NEXT (Near End Cross Talk) values from all aggressors.

Syed - 2
Fig. 1. Illustration of the main S-parameters of a Serial Link

Some standards will specify Channel Operation Margin (which is a simple limiting budgeting allocation on all the above parameters as shown in Fig. 1. In addition to this, limits on the trace differential impedance, differential-to-common mode s-parameters, or an Eye Mask may also be defined. It is important to remember that meeting these requirements increases the confidence level of successful link operation. Failure to meet them simply increases risk, introduces uncertainty in operation and an increased Bit Error Ratio (BER). A graceful degradation in performance, such as a need to operate at a lower data rate is more likely than a complete catastrophic failure.

III. Channel Physical Properties

syed - 3
Fig. 2: Illustration of PCB factors that affect s-parameters and the Eye Opening

Channel physical properties shown in Figure 2 have a direct impact on the s-parameters and the Eye diagram. PCB traces category includes (1) trace type which affects IL, (2) Trace Impedance which affects ILD and RL, (3) Trace coupling which affects IL, RL and ILD, (4) Trace thickness and surface roughness which affects IL, (5) Trace coating which affects IL, RL and Skew, (6) Trace bends which affect IL and Skew, (7) Trace spacing which affects ICR, (8) Trace reference planes which affects ILD, and the use of Trace coupons. PCB material affects IL and Skew. PCB vias affect RL, ILD and ICR. AC coupling capacitors affect IL, ILD and RL. The PCB stackup, connectors and BGA breakout affect all 5 parameters. Details of their influence will be presented with numerical examples where possible.
IV. Numerical Illustration and Conclusion

An illustration of the application is shown in Fig. 3 for a mid-plane system. The serial link traverses an orthogonal connector and the s-parameters of the link are shown in Fig. 4. The transmit and receive devices have output power control, pre-emphasis, amplification and adaptive equalization. Simulated Eye diagram with optimized device settings for 25 Gbps operation is shown in Fig. 5 and the eye opening has adequate margin for an error free operation. Design detail will be presented.

Syed 4
Fig. 3: Illustration of a mid-plane system

Syed 5
Fig. 4: s-parameters of a serial link in Figure 3

Syed 6
Fig. 5: 25 Gbps Eye diagram at the receiver


Syed Bokhari of Fidus Systems

[1] IEEE Std. 802.3ap™-2007 Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, Amendment 4: Ethernet Operation over Electrical Backplanes Approved 22 March 2007, IEEE-SA Standards Board (Amendment to IEEE Std 802.3™-2005)

February 25 – Kanata North BIA Networking Event

February 25, 2015, Ottawa, Canada

(L-R) Marianne Wilkinson (Councillor, Kanata North), Mayor Jim Watson, Peter Connolly (Fidus VP Business Development), Jenna Sudds (Executive Director, Kanata North BIA)

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Peter Connolly, VP of Business Development, attended the Kanata North BIA Networking Event on February 25, 2015. 


The KNBIA provided us with a great opportunity to network with our peers in the Kanata North Business Community, and learn more about the future direction of the KNBIA.

Highlights from the night:

MayorJenna Sudds, the Executive Director of the Kanata North BIA, gave a ‘State of the Nation’ report on the KNBIA.

Fidus Systems Inc. was presented as a new member of Kanata North following our recent move from our Bell’s Corners location. Fidus was highlighted during Jenna Sudds’ presentation.

Mayor Jim Watson gave everyone an update on the 2015 Initiatives within the City of Ottawa, Economic Development Activities, and the plans for 2017.

The Kanata North BIA provided the highlights of their Economic Development Projects for 2015.


Fidus looks forward to a having a productive, ongoing relationship with the KNBIA, and is excited to be a new part of the region!


February 10, 2015 – Mission to South Korea with Minister Ed Fast

2015-02-08 21.31.42-1Seoul, South Korea

(L-R) Jaemin Park (Sr. FPGA Designer), Michael Wakim (CEO)

Fidus has recently successfully showcased our 8K TV development system as a part of the Canada-Korea Free Trade delegation. Fidus met with many leaders in the tv/technology industry to highlight the future of television.

“Our development system allows engineers at the world’s foremost TV manufacturers to experiment with and address the bandwidth and computational challenges with 8K deployment. With our Japanese partner, Tokyo Electron Device we plan to play an important and supportive role in the future of 8K Television,” says Fidus CEO, Michael Wakim.

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“We see that 4K is already attractively priced for the consumer, but 8K isn’t far behind. The problem will be distribution, bandwidth and of course, content. Will it really make sense to create massive amounts of 4K content, and pay for the distribution network, if 8K TVs arrive at attractive price points before 4K is fully adopted?”8K television is the highest ultra high definition television to be in development today. With 16 times the resolution of HD TV, 8K Television will create an unrivaled viewing experience, and Fidus is very excited to be participating in it.

Fidus Systems Expanding in Ottawa and Waterloo

Ottawa, Canada – Ottawa-based Fidus Systems, a global leader in electronic product development  and consulting today announced relocation of their headquarters into larger 14,000 sq. ft. office and lab facilities at 375 Terry Fox Drive. The move follows the recent relocation of Fidus Kitchener into larger, 3500 sq. ft. office and lab facilities in Waterloo. Along with its San Jose, California facilities, the new space will increase total capacity to over 100 employees.
Since 2001, Fidus has designed products for over 300 customers involved in high performance computing, high speed communications, and high resolution video. For more information, please contact David Brown, VP, Sales Operations at

+1 (613) 595-0507.

November 10, 2014 – IEEE Ottawa EMC Distinguished Lecturer Presentation – Speaker Dr. Arun. K. Bhattacharyya

picture_arun_bhattacharyyaHosted jointly by the IEEE Ottawa EMC Chapter, the IEEE Ottawa MTT/AP Chapter and IEEE Ottawa CPMT Chapter

Speaker: Dr. Arun. K. Bhattacharyya, Distinguished Engineer, Northrop Grumman, Redondo Beach, CA
Topics: (1) Floquet modal based Analysis of Finite and Infinite Phased Array Antennas; (2) Efficient Shaped Beam Synthesis in Phased Arrays and Reflectors; (3) Advanced Horn structures for Reflectors and Phased Arrays

Organizers: Dr. Syed Bokhari, Chariman, IEEE Ottawa EMC Chapter;

Dr. Qingsheng Zeng , Chairman, IEEE Ottawa MTT/AP Chapter

Date: Monday November 10, 2014
Time: 6pm to 9pm
Location: Fidus Systems Inc. 35 Fitzgerald Rd. Ottawa ON K2H 1E6
Parking: Free in marked ‘Fidus’

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Floquet modal based Analysis of Finite and Infinite Phased Array Antennas

In this talk we present the Floquet modal analysis procedure for analyzing periodic array structures. The talk begins with a discussion on the relevance of Floquet analysis with regard to a scanned beam array design. Effects of mutual coupling on the performance of an array are discussed in details. It is shown how Floquet analysis can be employed to analyze a finite array with arbitrary amplitude taper including mutual coupling effects. A step-by-step procedure for aperture design is presented next. Method of analysis for an “array of subarrays” is also discussed. Design examples of patch and horn arrays are presented. A methodology for analyzing multilayered array structures with different periodicities is presented and applications of such structures in phased array antennas are discussed. In particular, characteristic features of a patch array loaded with a multilayered meander line polarizer are shown.

Efficient Shaped Beam Synthesis in Phased Arrays and Reflectors

Shaped beam array synthesis invites considerable attentions because arrays offer in-orbit reconfigurability, which is an attractive feature for communication and broadcasting satellites. In this talk, we present a brief overview of commonly used beam shaping algorithms. This is followed by the rojection Matrix Method of synthesis. The Projection Matrix method relies on orthogonal projection of the desired far field intensity vector onto the space spanned by the far field intensity vectors of the array elements. It is found that for a uniform convergence of the solution the far field sample space must be extended beyond the coverage region, otherwise the projection matrix becomes ill-conditioned. A general guideline for the far field sample space is provided. The method, with necessary amendments, is then employed successfully for a reflector surface synthesis. The method is found to be several times faster than the gradient search method commonly used for beam synthesis. Numerical results for array and shaped reflector syntheses are shown and the advantages are discussed.

Advanced Horn structures for Reflectors and Phased Arrays

In this talk we present an overview of various types of feed horns that are commonly used in single and multi-beam reflector systems and direct radiating arrays. The presentation begins with a discussion of smooth wall horns with single and multiple apertures, their operating principles, applications, advantages and their design procedures. In particular, the high aperture efficiency horns, both for rectangular and circular versions are discussed. The modal contents and generation of appropriate modes for achieving high aperture efficiency is presented. Potential applications of such horns in phased arrays and multi-beam reflectors are shown. Next, multiband horn structures using coaxial configuration and their applications are presented. This is followed by a presentation of various types of corrugated horns and their radiation characteristics. It is found that high Q resonances may occur in a corrugated horn within certain frequency bands where space wave and surface wave modes simultaneously propagate. A simple model is presented to demonstrate the resonance mechanism. Such resonances deteriorate the gain and cross-polar performances of a corrugated horn even if the return losses are acceptable at some resonant frequencies. Rectangular corrugated horns are more susceptible to these resonances than circular corrugated horns and the reasons are explained.



Arun K. Bhattacharyya received his B.Eng. degree in electronics and telecommunication engineering from Bengal Engineering College, University of Calcutta in 1980, and the M.Tech. and Ph.D. degrees from Indian Institute of Technology, Kharagpur, India, in 1982 and 1985, respectively.

From November 1985 to April 1987, he was with the University of Manitoba, Canada, as a Postdoctoral Fellow in the electrical engineering department. From May 1987 to October 1987, he worked for Til-Tek Limited, Kemptville, Ontario, Canada as a senior antenna engineer. In October 1987, he joined the University of Saskatchewan, Canada as an assistant professor of electrical engineering department and then promoted to the associate professor rank in 1990. In July 1991 he joined Boeing Satellite Systems (formerly Hughes Space and Communications), Los Angeles as a senior staff engineer, and then promoted to scientist and senior scientist ranks in 1994 and 1998, respectively. Dr. Bhattacharyya became a Technical Fellow of Boeing in 2002. In September 2003 he joined Northrop Grumman Space Technology group as a staff scientist, senior grade. He became a Distinguished Engineer which is a very rare and honorable recognition in Northrop Grumman. He is the author of “Electromagnetic Fields in Multilayered Structures-Theory and Applications”, Artech House, Norwood, MA, 1994 and “Phased Array Antennas, Floquet Analysis, Synthesis, BFNs and Active Array Systems”, Hoboken, Wiley, 2006. He authored over 95 technical papers and has 15 issued patents. His technical interests include electromagnetics, printed antennas, multilayered structures, active phased arrays and modeling of microwave components and circuits.

Dr. Bhattacharyya became a Fellow of IEEE in 2002. He is a recipient of numerous awards including the 1996 Hughes Technical Excellence Award, 2002 Boeing Special Invention Award for his invention of High Efficiency horns, 2003 Boeing Satellite Systems Patent Awards and 2005 Tim annemann Annual Quality Award, Northrop Grumman Space Technology.


MACOM, Xilinx, Fidus Systems and Inrevium Develop 12G-SDI FPGA Mezzanine Card

Xilinx’s FMC platform utilizes MACOM’s 12G-SDI Chipset to enable 4K60p video on a single channel, quadrupling video throughput and processing


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Lowell, MA, September 9, 2014 – M/A-COM Technology Solutions Inc. (MACOM), a leading supplier of semiconductor solutions for broadcast video infrastructure, announced today that Inrevium’s Xilinx-targeted FPGA Mezzanine Card (FMC) utilizes MACOM’s 12G-SDI Chipset to enable 4K60p video. Based on a collaboration with Fidus Systems and Inrevium, the solution supports the proposed 12G-SDI standard and quadruples the video throughput and processing that can be achieved on a single card.“12G-SDI is the next node on the evolution of the SDI standard. By entering into collaboration, Xilinx can now offer customers the ability to process 4K60p images with a single link connection, dramatically increasing the amount of video processing that can be achieved on a single card,” said Gary Shah, VP of Marketing, High Performance Analog, MACOM. “We are excited to deliver solutions that enable the broadcast industry to migrate to higher resolutions.”

“Our customers are developing 4K60p systems using Xilinx All Programmable FPGA and SoC devices. MACOM’s 12G-SDI components along with the Fidus/Inrevium 12G-SDI FMC provide a development platform that enables customers to process their video content through a single link,” said Aaron Behman, Segment Lead for the Broadcast Business at Xilinx.

MACOM’s family of 12G-SDI products are currently shipping in volume. These MACOM products, as well as the new 12G-SDI FMC card will be shown at IBC 2014 in booth 8.C01 (Hall 8) of the RAI convention center in Amsterdam.

For more information about IBC 2014, please visit

M/A-COM Technology Solutions Holdings, Inc. ( is a leading supplier of high performance analog RF, microwave, and millimeter wave products that enable next-generation Internet and modern battlefield applications. Recognized for its broad catalog portfolio of technologies and products, MACOM serves diverse markets, including high speed optical, satellite, radar, wired & wireless networks, CATV, automotive, industrial, medical, and mobile devices. A pillar of the semiconductor industry, we thrive on more than 60 years of solving our customers’ most complex problems, serving as a true partner for applications ranging from RF to Light.

Headquartered in Lowell, Massachusetts, M/A-COM Tech is certified to the ISO9001 international quality standard and ISO14001 environmental management standard. M/A-COM Tech has design centers and sales offices throughout North America, Europe, Asia and Australia.

MACOM, M/A-COM, M/A-COM Technology Solutions, M/A-COM Tech, Partners in RF & Microwave, The First Name in Microwave and related logos are trademarks of MACOM. All other trademarks are the property of their respective owners.

For more information about MACOM, please visit follow @MACOMtweets on Twitter; join MACOM on LinkedIn, or visit the MACOM YouTube Channel.

Xilinx is the world’s leading provider of All Programmable FPGAs, SoCs and 3D ICs. These industry-leading devices are coupled with a next-generation design environment and IP to serve a broad range of customer needs, from programmable logic to programmable systems integration. For more information, visit

Fidus Systems provides Electronic Product Development and Consulting Services across a wide range of industries. Focusing on high-speed, high complexity designs, Fidus enables your success with four design centers and flexible business models. Fidus delivers excellence in Hardware, FPGA, Signal Integrity, Embedded Software, RF, PCB Layout, and Mechanical design. Fidus is proud to be the inaugural Xilinx Alliance Program Premier Design Services Member in North America. Visit

Inrevium offers FPGA platform solutions, market specific IP, technical support, and design services to customers worldwide. inrevium is a Xilinx Alliance Program Premier Design Services Member and delivers the highest level of market and domain-specific expertise and pre-qualified solutions through Xilinx All Programmable platforms. The Design and Development Center uses its wealth of customer project experience and the latest equipment to provide specialized customer design services. The Development Center also creates market-specific multi-million gate LSI devices, FPGA evaluation boards, FMC option cards, ASIC prototyping boards, drivers, firmware, and IP to support a wide range of applications. For more information, please visit

Any express or implied statements in MACOM product announcements are not meant as warranties or warrantable specifications of any kind. The only warranty MACOM may offer with respect to any product sale is one contained in a written purchase agreement between MACOM and the purchaser concerning such sale and signed by a duly authorized MACOM employee, or, to the extent MACOM’s purchase order acknowledgment so indicates, the limited warranty contained in MACOM’s standard Terms and Conditions for Quotation or Sale, a copy of which may be found at:

North Americas — Phone: 800.366.2266
Europe — Phone: +353.21.244.6400
India — Phone: +91.80.43537383
China – Phone: +86.21.2407.1588

Husrav Billimoria
M/A-COM Technology Solutions Inc.

Colin Boroski
Rainier Communications
508-475-0025 x142

Gerlinde Knoepfle
embedded PR
+49 (0)89 64913634-12

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July 30, 2014 – IEEE Distinguished Lecturer Presentation hosted jointly by the IEEE Ottawa EMC Chapter, and the IEEE Ottawa MTT/AP Chapter

2014.07.22 IEEE Presentation Yihongss_smWednesday July 30, 2014
6:00 PM to 8:00 PM
Fidus Systems Inc.,35 Fitzgerald Road, Suite 400
Ottawa, ON,K2H 1E6

Speaker: Dr. Yihong Qi, Chief Scientist, General Test Systems Inc.
Topic: Over The Air Test for Wireless Systems
Organizer: Dr. Syed Bokhari, Chairman, IEEE Ottawa EMC chapter

Embedded Vision Summit West 2014 Achieves Record Attendance

Embedded Vision Alliance announces plans for 2015 Summit

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WALNUT CREEK, Calif., June 25, 2014
SOURCE Embedded Vision AllianceThe Embedded Vision Alliance ( today announced that nearly 500 product creators attended the recent Embedded Vision Summit West to learn about the latest in computer vision technology from leading technologists. Members of the Embedded Vision Alliance were thrilled at the record attendance and at the keen interest in their technology from attendees.

The Embedded Vision Summit West 2015 was held on May 29 at the Santa Clara Convention Center. Like previous Embedded Vision Summits, it was organized by the Embedded Vision Alliance to give engineers the practical information they need to design systems and applications that have the ability to see and understand. Chris Rowen, Fellow at Cadence Design Systems, an Embedded Vision Alliance Member company, observed, “Vision intelligence is becoming one of the primary interfaces for so many products—for the cloud, Internet of Things, and next-generation consumer products and mobile devices. The Summit is a wonderful convergence of so many different ideas, companies and trends. Not only is it a great place to catch up with what’s going on in computer vision, it’s become the place where people from other areas come to explore one of the grand challenges in semiconductors, system software, and design methodology.”

Attendees were impressed at the opportunities the Summit provided. Richard Neumann, founder of startup 2r1y, said, “We’ve made some amazing contacts here and I now see great opportunities for our company that I didn’t think existed when I got here this morning.”

Simon Morris, CEO of Alliance member CogniVue Corporation was unequivocal in his company’s support for the event, saying, “The Summit is one of the best places we can go to network with future customers and partners. In fact, half of the partners we have, we met at an Embedded Vision Summit. It’s really valuable as a focused event where we gain both partners and customers.”
The Alliance has also announced that the next Embedded Vision Summit will be held on April 30, 2015, at the Santa Clara Convention Center. Planning is under way for an expanded conference program, with business, introductory technical, and advanced technical tracks. The 2015 Summit will also include a bigger Technology Showcase, with demos of computer vision technology by industry innovators, as well as exciting keynote presentations by leading technologists.

The Embedded Vision Summit is organized by the Embedded Vision Alliance, an industry partnership that brings together providers of the technology used to create practical applications of computer vision. Founded in May 2011, the Alliance currently has 37 Member companies worldwide. Membership is open to any company that supplies hardware, software, or design services for computer vision systems and applications. To join the Alliance or participate in the 2015 Summit, contact the Alliance at

Media Contact:
Brian Dipert
+1 (530) 414-6908

Business Contact:
Jeremy Giddings
+1 (925) 954-1411

51st DAC “Take A Shot” contest results are in! 2014

EELive! Take A Shot

Fidus Systems hosted our famous “Take A Shot” contest at the 51st DAC Show in San Francisco from June 2-4, 2014.
Over 200 people took a shot

Challenge: How many 0805 resistors are in our 2 ounce shot glass?
Answer: 23, 547 resistors
Closest Guess: 24, 000
Runner Up: 23, 000

Well done folks!!
A big thank you to everyone who participated in our contest!